A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
Intel, Pentium, and i960 are registered trademarks of Intel Corporation. StrongARM is a trademark of Advanced RISC Machines, Ltd. IxWorks is a trademark of Wind River Systems. I2O SIG is a trademark of the I2O Special Interest Group. Alpha is a trademark of Compaq Computer Corporation. ClearPath is a trademark of Unisys Corporation.
1. Field of the Invention
The present invention is directed to computer systems, and more particularly, to methods, apparatus, and computer program products for transferring data between computer system elements in multiple buffers. In general, the present invention addresses situations where the size of the source and destination buffers is fixed, but the source buffer size differs from the destination buffer size.
2. Description of the Prior Art
Data transfers from one memory to another memory in a computer system, particularly where the formats of the two memories differ, sometimes require that a pad (i.e., some pattern of data) be inserted periodically after successive portions of the data are transferred. Other transfers require the removal of this pad as the transfer takes place. Typically, the pad helps to bridge the incompatibilities between memory formats. For example, copending, commonly assigned application Ser. No. 09/144,300, filed Aug. 31, 1998 now abandoned, entitled xe2x80x9cImproved Method For Providing Variable Sector-Format Operation To A Computer Systemxe2x80x9d describes a technique in which padding is used to enable a Unisys ClearPath HMP NX enterprise server, which stores data in its internal memory in logical sectors of 180 bytes, to transfer a buffer of data to an attached storage device in which data is arranged in physical sectors of 512 bytes. The Unisys ClearPath HMP NX enterprise server runs under the control of the Unisys MCP operating system and is sometimes also referred to as an MCP server.
FIG. 1 illustrates the padding technique described in the copending application. In the example shown, assume that it is desired to write four logical sectors of data from an application program buffer 10 in an MCP server 12 to an attached storage medium, such as a disk 14, having a physical sector format that differs in size from the logical sectors in the memory of the MCP server. Specifically, in this example, only two logical sectors will fit within one physical sector, leaving a portion of the physical sector unfilled. According to the method described in the copending application, this mismatch between formats is handled by transferring successive pairs of logical sectors to the storage medium, each followed by a pad of data (152 bytes) that fills out the remainder of the respective physical sectors into which the pairs of logical sectors are stored.
More specifically, the MCP server 12 will make a write request addressed to logical sector 0 of the buffer 10, with a specified length of four logical sectors. The logical sector request is mapped to the corresponding physical sectors of the disk 14xe2x80x94in this example, physical sectors 0 and 1. The input/output subsystem of the MCP server 12 will begin the transfer (step 16) by writing logical sectors 0 and 1 to physical sector 0 of the disk. The I/O subsystem will then automatically insert a pad of data (the striped area following logical sector 1) to fill-out the remainder of physical sector 0 (step 18). Then, logical sectors 2 and 3 will be written to the next physical sector (step 20), again automatically followed by a pad of data to fill-out the remainder of that physical sector (step 22).
In general terms, the kind of transfer illustrated in FIG. 1 can be described as the transfer of a buffer of data of length L from a first memory (e.g., main memory) to a second memory (e.g., disk 14), wherein a pad of length P is inserted after each successive portion of length S of the data is transferred. In the example of FIG. 1, the length S of each successive portion of data transferred is 360 bytes (i.e., two logical sectors) and the length P of the pad is 152 bytes (i.e., the size of the remaining unfilled portion of each physical sector). The need for this kind of transfer exists in numerous other computer systems for a variety of reasons, and the foregoing is just one example.
In Unisys ClearPath HMP NX enterprise servers, the capability to insert a pad after successive portions of a buffer of data are transferred is implemented in hardware. FIG. 2 is a block diagram illustrating the basic architecture of a ClearPath HMP NX enterprise server. As shown, a main memory 24 is coupled to a memory interface unit (MIU) 30 via a memory bus 28. The MIU 30 is coupled to several other processors via an internal bus 32. The other processors include an input/output unit (IOU) 34, a channel management unit (CMU) 36, and a data transfer unit (DTU) 38. The CMU 36 is further connected to an I/O channel adapter 40. A peripheral unit 42, such as a disk drive or other secondary storage medium, connects to the I/O channel adapter 40. It should be noted that in addition to IOU 34, which is an input/output unit, the entire module, including the MfU 30, the IOU 34, the CMU 36, and the DTU 38 is referred to as an input/output module (IOM).
The MIU 30 provides the interface between the above mentioned processors and units and the main memory 24. The MIU 30 handles the buffering and issuing of addresses to main memory 24 for store and fetch operations. The MWU 30 also handles translation between logical and physical addresses and arbitration of a plurality of requests from the memory 24.
The CMU 36 manages data movement between the main memory 24 and any peripheral I/O units (e.g., disks and tape drives) which may be coupled to the processing system. The CMU 36 communicates with external channels, such as the channel adapter 40, through a channel service bus (not shown). The DTU 38 controls block data transfer from one location in main memory 24 to another upon the request of the IOU 34. The DTU 38 is also used for disk caching.
The IOU 34 performs high level I/O functions, such as the scheduling of I/O jobs, the selection of data paths over which I/O jobs are performed, the gathering of job statistics, and the management of I/O devices and of a disk cache. The IOU 34 determines whether padding is required during transfer of a buffer of data from main memory to a peripheral unit 42, such as a disk drive. For example, the IOU 34 detects when a disk unit having a 512 byte physical sector format is attached to the channel adapter 40 and programs subsequent data transfers to the disk unit so that the padding method illustrated in FIG. 1 is employed. The actual padding operation is carried out by proprietary hardware on the channel adapter 40. Specifically, the hardware on the adapter is programmable to insert P bytes of data after every S bytes of data is transferred from the main memory 24 to the peripheral unit 42.
Today, there is an ever increasing push for companies in the computer industry to supply systems that are built using industry standard components, relying less on proprietary designs. One area in which this trend is strong is input/output processing. There have been a number of industry-wide initiatives to develop standard specifications for the design and operation of input/output devices and subsystems. For example, the computer industry has recently begun to adopt and to implement solutions based on the Intelligent I/O (I2O) Architecture Specification, which describes standard specifications for the development of intelligent I/O adapters and associated device driver software.
FIG. 3 is a block diagram illustrating a typical computer system configuration based on more common industry standards. As shown, the typical computer system comprises a central processing unit (CPU) 50 and a main memory 52 that communicate over an internal system bus 54. The CPU 50 may be implemented using any of a number of microprocessors available from various companies, including, for example, Intel(copyright) Pentium(copyright) processors, Compaq/DEC Alpha microprocessors, etc. Some systems may comprise more than one CPU 50. An I/O bridge 56 interfaces the system bus 54 to an input/output bus 58. The input/output bus is typically based on an industry standard specification, such as the Peripheral Component Interconnect (PCI) specification. The system may also have one or more adapter cards connected to the input/output bus 58. FIG. 3 shows a so-called xe2x80x9cintelligentxe2x80x9d input/output adapter 60 that can be used to provide an interface between the input/output bus 58 of the computer system and some peripheral input/output device 70. The input/output adapter 60 typically includes a memory controller 62, such as a Direct Memory Access (DMA) controller, that handles the transfer of data from the main memory 52 of the computer system to the peripheral device 70. xe2x80x9cIntelligencexe2x80x9d is usually provided by an embedded processor 64, such as an i960(copyright) or StrongARM(copyright) processor available from Intel Corporation, and an associated local memory 66, both of which are attached to a local bus 72 on the adapter 60. Some sort of device interface 68 provides the necessary interface circuitry to the peripheral device 70. For example, the device interface circuitry 68 might comprise a PCI-to-SCSI conversion to enable Small Computer Systems Interface (SCSI) peripherals to be attached to the computer system 51 via the adapter card 60.
Although the use of industry standard components in an adapter card offers the advantages of lower cost and wider interoperability with the hardware of other vendors, functionality may be limited by the capabilities of the available, industry-standard components. This can be problematic in situations in which a vendor that previously relied upon proprietary solutions to provide certain functionality must now offer similar functionality using industry-standard components that may not directly support that functionality.
The ability to pad data during transfers from one memory to another, as illustrated by way of example FIG. 1, is one example of functionality that typically is not found in current industry-standard input/output components, such as Direct Memory Access (DMA) controllers and the like. As mentioned above, Unisys corporation has provided this capability in the past using proprietary hardware components. Consequently, there is a need for methods and apparatus for inserting a pad of data of length P after successive portions of a buffer of data are each transferred from a first memory to a second memory, which methods and apparatus are not limited to implementation via proprietary designs. Additionally, it would be desirable if any such methods and apparatus could achieve the desired padding with minimal additional processing overhead. The present invention satisfies this need.
The present invention is directed to methods and apparatus for transferring a buffer of data of length L from a first memory to a second memory such that a pad of length P is inserted after each successive portion of length S of the data is transferred. More specifically, in accordance with the present invention, a scatter-gather list is generated and then used to control the transfer of a buffer of data such that a pad of length P is effectively inserted after each successive portion of length S of the data is transferred. For transfers in the reverse direction, the pad is stripped.
In one embodiment of a method of the present invention, a scatter-gather list is generated that comprises two scatter-gather list elements for each successive portion of length S of a data buffer to be transferred. The number of successive portions of length S in a buffer of length L can be expressed as: (L+(Sxe2x88x921)) DIV S. In this embodiment, the first element for a given successive portion of length S specifies the transfer of that portion (e.g., by indicating the start of that portion and a length for the transfer of S). The second scatter-gather list element for that portion of the buffer specifies the transfer of a predetermined memory location of length P (i.e., the length of the desired pad). Preferably, the predetermined memory location that is used to define the pad is the same for each successive portion of length S of the data. In an embodiment wherein the present invention is implemented in an input/output adapter having a local memory, the predetermined memory location that is used to define the pad preferably resides in the local memory. In other embodiments, however, the predetermined memory location could be defined elsewhere, such as, for example, in the main memory of a computer system.
In another embodiment of the method of the present invention, a scatter-gather list is generated that comprises only one scatter-gather list element for each successive portion of length S of a data buffer to be transferred. Again, the number of successive portions of length S in a buffer of length L can be expressed as: (L+(Sxe2x88x921)) DIV S. In this embodiment, each scatter-gather list element specifies a transfer that starts at the beginning of its respective portion and has a length of S plus P (length=S+P). For each scatter-gather list element, the first S words to be transferred constitute the actual data and the last P words form the required pad. Because each successive portion and its respective pad are transferred using a single scatter-gather list element in this embodiment, the desired result is achieved using half the number of scatter-gather list elements as the previously described embodiment.
An input/output adapter in accordance with the present invention comprises a memory controller of a type capable of transferring data in accordance with a scatter-gather list, and a processor for generating a scatter-gather list to control the transfer of a buffer of data from a first memory to a second memory such that a pad of length P is inserted after each successive portion of length S of the data in the buffer is transferred to the second memory. The scatter-gather list may be generated by the processor in accordance with either of the embodiments described above.
Preferably, the processor is made to function in accordance with the present invention by executing program code stored on a computer-readable medium, such as, for example, a read-only-memory coupled to the processor. Again, the program code may implement either of the embodiments of the method described above in generating the required scatter-gather list. As stored on such a computer-readable medium, the program code forms a computer program product.
Additional features and advantages of the present invention will become evident hereinafter.